1. Field of Invention
This invention pertains generally to semiconductor memory devices and, more particularly, to a self-aligned split-gate flash memory and process of fabricating the same.
2. Related Art
Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's) and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 1.0-2.0 volts after an erase cycle, which adds complexity to the circuit design.
Although a split-gate memory cell has no over-erase problem, it generally includes an additional gate known as a select gate. Such cells are typically fabricated in double-poly or triple-poly processes which involve relatively complex processing steps. In addition, split-gate cells are generally larger than stack-gate cells. Nevertheless, because of the relatively simple circuit design which is possible when there is no over-erase problem, split-gate cells are used widely, particularly in embedded nonvolatile memory applications.
U.S. Pat. Nos. 6,091,104 and 6,291,297 disclose a split-gate memory cell of relatively small size, with efficient erase performance and a small programming current, and a portion of an array of such cells is illustrated in FIG. 1. Each cell has a floating gate 21 and a control gate 22 which are stacked vertically, with the control gate above the floating gate. A select gate 23 is positioned to one side of stacked gates. Source regions 24 are formed in substrate 26 between the floating gates in adjacent pairs of cells, and a drain region 27 is formed in the substrate between the select gates. A bit line 28 is connected to the drain region by a bit line contact 29.
In the program mode, the control gate is biased at a voltage of about 10 volts, the select gate is biased at −2 volts, and the source is biased at 6 volts. A relatively high positive voltage is coupled from the control gate to the floating gate, and a strong electric field is established across the mid-channel gate oxide 31 between select gate 23 and floating gate 21. This causes electrons to accelerate and inject into the floating gate.
In the erase mode, a negative voltage of about −9 volts is applied to the control gate, and a positive voltage of about 6 volts is applied to the select gate. This produces a strong electric field across the inter-poly oxide 32 between the select gate and the rounded edge of the floating gate, which initiates Fowler-Nordheim tunneling, with electrons migrating from the floating gate to the select gate.
Even though this approach permits in a smaller cell size than the widely used ETOX technology, the need for a select gate in addition to the stacked control and floating gates limits its utility as cell sizes continue to decrease toward hundreds of nanometers.